1. Technical Field
The present invention relates in general to preventing data errors in processors and in particular to preventing data errors created by false transitions occurring as a result of capacitively coupling of interconnects. Still more particularly, the present invention relates to a method of classifying and arranging interconnects within processor execution units so that quiet lines are created between adjacent interconnects when transmitting signals.
2. Description of the Related Art
In complicated reduced instruction set computing (RISC) processor architectures, large numbers of interconnect wires cover and connect the various circuit elements. Many of these interconnect wires run parallel for significant distances, and are therefore subject to noise from capacitive coupling. FIG. 7A depicts an isometric view of four levels of metallization within an integrated circuit. odd numbered wire levels, level one interconnects 710-716 and level three interconnects 730-736, are perpendicular to even numbered wire levels, level two interconnects 720-726 and level four interconnects 740-746. However, interconnects on a particular level are parallel to each other and to interconnects two levels above or below. Therefore, as illustrated in FIG. 7B, which depicts a cross-sectional view of the metallization levels shown in FIG. 7A, parasitic capacitances exist between parallel, adjacent interconnects on the same level (between metal one interconnects 710-712, 712-714, and 714-716, and between metal three interconnects 730-732, 732-734, and 734-736) and between adjacent interconnects which are two levels apart (between metal one interconnect 710 and metal three interconnect 730, between metal one interconnect 712 and metal three interconnect 732, between metal one interconnect 714 and metal three interconnect 734, between metal one interconnect 716 and metal three interconnect 736, and between metal two interconnect 720 and metal four interconnect 740). Capacitances between interconnects on the same level are typically about twice as large as capacitances between interconnects which are two levels apart. A circuit diagram of parallel interconnects within a single metal level (level one of FIG. 7A seen from a plan view) is illustrated in FIG. 7C. Capacitive coupling between parallel interconnects 710-716 may create RC time delays and may be significant to switch transistors at the ends of the interconnects.
Capacitive coupling of metal interconnects may result in false signal transitions, and is therefore of particular concern in dynamic circuits, which are designed for only one transition per cycle, and self-timed circuits, which are designed for only one transition per evaluation window. This problem of false transitions resulting from capacitive coupling may be understood by reference to dynamic circuits and their operation. For example, a typical "domino" dynamic circuit is depicted in FIG. 8, which is a circuit diagram for a single rail buffer. When reset input r_in goes low, p-channel transistor QR3 is turned on, bringing node I2 connected to the gate of n-channel transistor QF5 up to the power supply voltage V.sub.DD. Transistor QF5, in turn, pulls the output d_out down to the ground voltage GND. Stand-by p-channel transistor QS4, which is connected at the gate to output node d_out, is thus turned on. When reset input r_in goes high while data input d_in is inactive or low, stand-by device QS4 will hold node I2 and the gate of transistor QF1 at the power supply voltage V.sub.DD, preventing any charge leak off due to junction leakage and/or subthreshold conduction.
When data input d_in subsequently goes high, transistor QF1 is turned on and discharges node I2 to ground, over-driving weak stand-by device QS4. The gates of transistors QF5 and QF6 are thus pulled to ground, turning off transistor QF5 and turning on p-channel transistor QF6. Output d_out is therefore pulled high by output driver QF6. Output d_out thus tracks data input d_in when reset input r_in goes high after having been low.
Foot transistor QR2 is provided to interrupt the path from node I2 through transistor QF1 to ground GND when reset input r_in goes low. This forces output d_out to ground GND even if data input d_in is active when reset input r_in is driven low. Foot transistor QR2 is thus optional an may be eliminated if the design guarantees that data input d_in is always inactive when reset input r_in is low. Furthermore, it should be noticed that transistor QF1 may be replaced by any n-channel transistor combination implementing a boolean expression. Although a single rail buffer is shown, the circuit may also be implemented as a dual rail circuit.
The operation of a dynamic circuit such as that depicted in FIG. 8 may generally be divided into three parts: the reset phase, the standby phase, and the evaluation phase. These operational phases (or states) are illustrated in the timing diagram of FIG. 9. Typically all outputs of the dynamic circuit go low during the reset phase, when reset input r_in goes low in the case of the circuit depicted in FIG. 8. For dual rail circuits, both outputs are generally low as a result of the reset being asserted. Upon removal of the active reset signal, the circuit enters the stand-by phase, during which it is awaiting input data. As the input data arrives at the data input d_in, the circuit begins its evaluation phase.
The circuit depicted in FIG. 8 enters the reset phase or state when reset input r_in goes low, turning on transistor QR3 to charge node I2, and turning off foot transistor QR2 to interrupt the path from node I2 through transistor QF1 to ground GND in case data input d_in is active. The circuit enters the standby phase when reset input r_in goes high, turning off transistor QR3, turning on foot transistor QR2, and turning on stand-by transistor QS4. While data input d_in is inactive, the charge at node I2 is maintained by stand-by device QS4, and transistor QF5 continues to pull the output d_out to ground GND. Because a foot device QR2 is employed and data input d_in is permitted to be active during the reset phase, the stand-by phase is optional for the circuit depicted in FIG. 8.
The evaluation phase is entered when the data arrives at data input d_in after the reset phase is complete. If the data signal received at data input d_in is low, output d_out remains low. If data input d_in goes high, however, once reset input r_in goes high device QF1 is turned on an node I2 is discharged to ground. Device QF5 is turned off, output driver device QF6 is turned on, and output d_out is pulled to the power supply voltage V.sub.DD.
It should be observed from FIGS. 8 and 9 that output d_out is low during both the reset phase and the standby phase, and is active (if at all) only during the evaluation phase. Thus, there are two distinct quiet levels at the output during the operational phases of a dynamic circuit. Capacitive coupling between metal interconnects driven by the outputs of dynamic circuits will therefore only occur, if at all, during the low-to-high transitions in the evaluation phase or the high-to-low transitions of the reset (precharge) phase of the dynamic circuits driving the interconnects.
It would be desirable, therefore, to provide a method and apparatus for avoiding capacitive coupling of interconnects within a processor employing dynamic circuits. It would further be advantageous to utilize the quiet levels of dynamic circuits to avoid capacitive coupling of interconnects attached to the outputs of the dynamic circuits.